Current trends in IC chip design have ever increasing power demands. For example, desire for better performance, higher levels of integration and smaller dimensions results in higher processor frequency and increasingly complex logic with higher density and higher switching activity. This increased demand for power, has led to corresponding efforts to reduce power consumption.
One approach to reducing power consumption is to reduce the operational voltage of the chip. However, as the operational voltage decreases, propagation delays through the transistors increases. Though the threshold voltage can be reduced to help maintain the required performance, decreasing the threshold voltage increases the total leakage power. Therefore, there is a limit to this approach.
Another approach reduces clock speeds. This of course, similarly, limits performance.
In addition, there are situations where new applications have the potential to consume higher power than the circuits on which they run were designed. If execution of a new application causes power consumption to exceed circuit limits, the system could shut down. For many applications this is simply unacceptable.
As will be appreciated, accurately controlling the power consumption state of an integrated is most effective when the current power consumption can be accurately assessed. As such, new methods and circuits for estimating and adapting power consumption of IC chips in real-time are desirable.